The market for high density electronic circuit packages of multiple semiconductor chips continues to increase. Two common types of semiconductor chip stacks are the vertically-extending (or "pancake") stack and the horizontally-extending (or "breadloaf") stack.
U.S. Pat. Nos. 4,525,921 and 4,646,128 by Carson et al. disclose structure and fabrication techniques for producing one type of high density, multichip electronic package. These documents describe a semiconductor chip stack consisting of multiple integrated circuit chips adhesively secured together. A metallized pattern is provided on at least one side surface of the stack for electrical connection of the stack to external circuitry. This metal pattern typically includes both individual contacts and bussed contacts. The stack is positioned on an upper surface of a substrate so that electrical contact can be made between the stack metallization pattern and a substrate surface metallization pattern.
Various alternate stack structures and electrical interconnection possibilities have also been described. For example, reference U.S. patent application Ser. No. 08/000,826 entitled, "Multichip Integrated Circuit Packages and Systems," U.S. patent application Ser. No. 08/120,876, entitled "Integrated Multichip Memory Module, Structure and Fabrication," and U.S. patent application Ser. No. 08/120,993, entitled, "Integrated Memory Cube, Structure and Fabrication," which are all commonly assigned to the same assignee as the present invention, and which are all hereby incorporated herein by reference.
At least one redundant chip(s) is often provided in a semiconductor chip stack so that if one or more of the primary chips in the stack should fail following stack fabrication and/or stressing (i.e., burn-in), the redundant chip(s) may be "invoked" to provide the electronic circuit package with the desired performance level. This activity is referred to in the art as "sparing." Invoking of a redundant or spare semiconductor chip is typically physically accomplished at the package level of assembly, which normally entails wirebonding the chip to a lead frame and then encapsulating the entire assembly in a polymer material. Thus, burn-in and invoking of the redundant semiconductor chip ("sparing") in a multichip package must be performed prior to encapsulation and final testing of the semiconductor chip stack. Unfortunately, chip failure can occur during final stack packaging, in which case the resultant electronic circuit package must be discarded.
Conventional stack "breadloaf" sparing technology is based on provision of a programmable via in combination with a thin film metallization layer on a side-surface of an unpackaged semiconductor chip stack. Such technology enables access to the spare chip(s) in the stack while still maintaining a fixed pattern and fixed function solder bump array. Alternatively, additional stack side-face wiring channels may be employed to independently access a spare chip(s) in the semiconductor chip stack.
An important application of today's chip stacking technology is in the fabrication of computer memory systems. Traditionally, computer memory systems are assembled from many types of memory chips, such as DRAMs, SRAMs, EPROMs and EEPROMs. The number of storage devices per memory chip technology generation varies but increases over time with more devices per chip being delivered with each succeeding generation, thereby providing greater memory capacity. When a next generation memory chip becomes available, the number of chips needed to make a given memory system is correspondingly reduced. With fewer memory chips needed, the resultant memory system becomes physically smaller.
The next generation DRAM memory chips have traditionally increased by 4.times. the number of bits compared with current generation technology. For example, assume that the current generation of memory chips comprises 16 megabit (Mb) chips, then by industry standards the next generation comprises 64 Mb memory chips. This 4.times. advancement from one generation of memory chips to the next generation is typically accomplished with corresponding advancement in semiconductor tool and process technologies, for example, sufficient to attain a 2.times. reduction in surface geometries. Due to this interrelationship, a significant interval of time can pass between generations of memory chips. Therefore, a genuine improvement in memory system design and fabrication would be attained if current generation memory chips could be assembled to have the same functions and physical dimensions of an anticipated, next generation memory chip. The multichip memory packages and fabrication techniques presented in the above-incorporated patent applications provide such an improvement.
Experience has shown that burn-in stressing of semiconductor chips in a multichip package predominately results in only a few single bit (i.e., "memory cell") fails per failing semiconductor chip. For example, in a typical failed memory chip, there might be 10-15 memory cells in the chip which fail testing following burn-in stressing. Currently, there is no cost-effective technology to spare only these failed bits, particularly after the chip has been encapsulated; that is, at least not without providing a redundant semiconductor chip. Therefore, an entire semiconductor chip stack might have to be discarded because of only a few failed memory cells. Since single memory cell failures are the predominant mode of failure of a semiconductor chip's memory, an alternative stack sparing approach based on replacement of only the failed memory cell(s), rather than replacement of the entire semiconductor chip, would clearly have commercial advantages.
As another problem, most semiconductor random access memories (RAMs) utilize power-on latches which assume a state based on non-volatile data. Fuses, for instance, can be opened to influence latch state during power-up. Such circuit technologies are commonly used for memory array redundancy allocation. Unfortunately, in a high radiation flux environment, an ion impact episode may cause these redundancy latches to flip; thereby activating or deactivating random redundancy. Obviously, this could have catosphropic consequences to a memory dependent machine.
In general, various novel techniques for providing programmable sparing capability to a multichip package, either with or without the inclusion of a spare chip(s) in the multichip package, are presented herein. These techniques address each of the above-noted drawbacks of the existing multichip stack fabrication art.